Semiconductor disk devices, such as a USB memory, using a flash memory, are widely used in recent years. Semiconductor disk devices are requested to have higher capacity, higher speed, and more power saving according to the expansion of its use. Flash memories have different characteristics from DRAMs in some respects. For example, on writing data to a NAND-type flash memory, the area to which the data is to be written must be erased beforehand. The erasing process requires very long time as compared with a reading process. Moreover, flash memories become inoperative when the number of accesses reaches a specified limit.
To cope with such characteristics of flash memories, it is desirable to combine multiple accesses to a flash memory into a single access. One technique that combines multiple accesses to one is access command buffering. For example, two or more write commands for a flash memory are temporarily stored in a buffer, and the write commands to one sector are combined to one write command, and then issued to the flash memory. However, the amount of data to be written varies in each write access. Therefore, it is difficult to make use of the full capacity of the buffer so as to store a large number of commands efficiently.
Furthermore, a cache memory of CPU may be used to execute a plurality of accesses at one time. However, the cache memory of CPU is primarily used to increase memory access speed, not to decrease the number of accesses to the main memory. For this reason, it does not work well for flash memories.
The objective of this invention is to provide a memory apparatus, method, and program for solving the above-mentioned problems. The objective is attained by combinations of the features described in the independent claims. The dependent claims specify further advantageous examples of the invention.